This invention relates to multimode multiplier circuitry for integrated circuits such as programmable logic devices and to methods for designing, verifying, and using multimode multiplier circuitry.
Multiplier circuits are used in a variety of integrated circuits for functions such as digital signal processing. Multimode multipliers can be configured to operate in more than one mode of operation. For example, a duplex multiplier can be configured to operate in two different modes. In the first mode, a duplex multiplier operates as a single large multiplier. In the second mode, the duplex multiplier operates as two smaller multipliers. An 18×18 duplex multiplier may be configured to operate either as a single 18-bit×18-bit multiplier or two 9-bit×9-bit multipliers. Because multiplier circuits consume a relatively large amount of circuit resources, it is more efficient to implement the 18×18 and 9×9 capabilities in a single duplex multiplier, rather than providing three separate multipliers (one 18×18 and two 9×9) on an integrated circuit.
The mode of operation of a multimode multiplier can be selected by a user of the integrated circuit (i.e., a logic designer). For example, in a programmable logic device or a digital signal processing chip with configurable logic, a control bit may be set to configure a duplex multiplier as either a single 18×18 bit multiplier or two 9×9 bit multipliers depending on the needs of the user. Both 18×18 and 9×9 multiplication functions cannot be used simultaneously, but because of the improved efficiency of using shared hardware to implement both 18 bit and 9 bit functions, duplex multiplier designs are the preferred solution in many situations.
Many integrated circuits are designed using libraries of standard cells. The standard cells are circuit building blocks containing generic components (e.g., NAND and NOR gates, flip-flops, etc.). Software design tools are available to assist logic designers in designing complex circuits based on standard cells.
The design tools allow a logic designer to input logic designs using a high-level hardware description language (HDL) such as Verilog. At the highest level, the designer's HDL specification is generally provided as a register-transfer level (RTL) model. Using a logic synthesis tool and various other design tools, the logic designer's RTL model is translated into an actual mask set for fabricating an integrated circuit containing the logic designer's required circuitry. In addition to logic synthesis, the logic design tools implement operations such as placement, physical optimization, and routing.
To ensure that a logic design is free of errors, logic designers may run vector-based simulations that attempt to thoroughly exercise a given logic design by examining the response of the logic to various test inputs. However, for large circuits such as 18-bit×18-bit multipliers, it is not practical to exhaustively exercise the entire design, because billions of test vectors would be required. Even if sets of test vectors are chosen carefully, full confidence in the correctness of a given design cannot be achieved, because it is not practical to test every possible vector.
To overcome the shortcomings of logic-simulation-based testing, logic equivalency checking (LEC) tools have been developed. LEC tools use canonical representations of combinatorial logic such as binary decision diagrams and can exhaustively test many logic designs that would be impractical to check using logic simulation techniques.
General purpose error checking algorithms such as those based on binary decision diagrams cannot be used to verify the proper operation of large multiplier circuits due to their complexity. As a result, dedicated multiplier testing algorithms (“solvers”) have been developed that will check standard multiplier designs for errors. For example, LEC tools are available with solvers that may be used to check standard 18-bit×18-bit multipliers for errors.
Because of their complexity, logic synthesis tools are unable to successfully synthesis duplex multiplier circuits from an RTL model without dividing the multiplier. For example, an attempt to perform synthesis on a conventional RTL model of an N×N duplex multiplier would result in the synthesis of three separate multiplier circuits—one N×N multiplier and two N/2×N/2 multipliers. Moreover, it is not possible to use an RTL model of a duplex multiplier for error checking, because there are no logic equivalency checking tools available that can perform this operation for duplex multiplier circuits. If a duplex multiplier is required for a given integrated circuit, incomplete and time-consuming logic simulation techniques must be used for error checking.
It would therefore be desirable to provide multimode multipliers whose operation can be exhaustively verified and to provide ways in which to design, verify, and use such multimode multipliers.